Apparatus and method for information processing

ABSTRACT

An information processing apparatus includes a first processor and a second processor. The first processor is operable to perform first processing and second processing in one of a plurality of operating states. The operating states includes a normal state and a power-saving state. The power-saving state is a state in which the first processor consumes less power than the normal state. The second processor is operable to perform the second processing while consuming less power than the first processor does. The second processor detects the first processing that the second processor is not able to perform. The second processor also causes the first processor to transition from the sleep state to the power-saving state to perform the first processing when the first processor is in a sleep state in which a power supply is stopped.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is based on and claims priority pursuant to 35U.S.C, § 119(a) to Japanese Patent Application No. 2016-092691, filed onMay 2, 2016, in the Japan Patent Office, the entire disclosure of whichis hereby incorporated by reference herein.

BACKGROUND Technical Field

Embodiments of the present disclosure relate to an informationprocessing apparatus and method.

Related Art

In recent years, processors, such as the central processing units (CPUs)used in information processing apparatuses, consume a large amount ofpower due to a high integration density. Accordingly, the processors, orthe information processing apparatuses generally have a power-savingfunction.

A power-saving state induced by the power-saving function includes asleep state, in which power supply to the processor is stopped. Toreduce the amount of power consumption, the processors are desirably inthe sleep state as long as possible. In view of this, some informationprocessing apparatuses include, in addition to a main processor, asub-processor that processes some data that can be processed with acomparatively light load relative to other data.

SUMMARY

An information processing apparatus includes a first processor and asecond processor. The first processor is operable to perform firstprocessing and second processing in one of a plurality of operatingstates. The operating states includes a normal state and a power-savingstate. The power-saving state is a state in which the first processorconsumes less power than the normal state. The second processor isoperable to perform the second processing while consuming less powerthan the first processor does. The second processor detects the firstprocessing that the second processor is not able to perform. The secondprocessor also causes the first processor to transition from the sleepstate to the power-saving state to perform the first processing when thefirst processor is in a sleep state in which a power supply is stopped.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

A more complete appreciation of the disclosure and many of the attendantadvantages and features thereof can be readily obtained and understoodfrom the following detailed description with reference to theaccompanying drawings;

FIG. 1 is a diagram illustrating an example configuration of an imageforming apparatus according to an embodiment of the present disclosure;

FIG. 2 is an illustration of a state transition of a main centralprocessing unit (CPU) in the embodiment:

FIG. 3 is a diagram illustrating an example of change in an amount ofpower consumption of the main CPU over time; and

FIG. 4 is a flowchart illustrating an overall process performed by a subCPU.

DETAILED DESCRIPTION

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the presentdisclosure. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“includes” and/or “including”, when used in this specification, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof. In describing preferred embodimentsillustrated in the drawings, specific terminology is employed for thesake of clarity. However, the disclosure of this patent specification isnot intended to be limited to the specific terminology so selected, andit is to be understood that each specific element includes all technicalequivalents that have the same function, operation in a similar manner,and achieve a similar result.

FIG. 1 is a diagram illustrating an example configuration of an imageforming apparatus 1, which is an example of an information processingapparatus, according to an embodiment. The image forming apparatus 1 isa multifunction peripheral (MFP) that can serve as a copier, a printer,a digital reading device/scanner, and a facsimile machine. The imageforming apparatus 1 is additionally performs communication via such as anetwork 30 and processes data obtained through the communication.

As illustrated in FIG. 1, the image forming apparatus 1 includes acontroller 11, an eco switch 12, a main power supply switch 13, a powersupply unit (PSU) 14, a central power supply switch 15, a control panel16, a facsimile communication device (fax) 17, a data storage device 18,an image reading device 19, and an image forming device 20.

The controller 11 controls the entire operation of the image formingapparatus 1. The eco switch 12 is an operating device that instructstransition of a power state of the image forming apparatus 1. The ecoswitch 12 is connected to the controller 11. A user's operation to theeco switch 12 allows the image forming apparatus 1 to transition betweena normal state and a power-saving state.

The main power supply switch 13 is an operating device that suppliespower provided from an external power supply (e.g. commercial powersupply), and stops supplying the power. The PSU 14 is a device thatgenerates alternating current (AC) power and direct current (DC) powerto be provided in the image forming apparatus 1, using the powersupplied from the external power supply.

The central power supply switch 15 causes the controller 11 to control apower state of each of the components 16 to 20. The central power supplyswitch 15 includes at least five power supply switches 15 a toindividually manage the power supply to each of components 16 to 20.

The control panel 16 allows the user to directly input data (includingvarious types of instructions, here) to the image forming apparatus 1.As illustrated in FIG. 1, the control panel 16 includes a centralprocessing unit (CPU) 115, a memory 116, a display 117, and a set ofkeys 118.

The memory 116 includes, for example, a read only memory (ROM) and arandom access memory (RAM). The display 117 includes, for example, aliquid crystal display (LCD) and a touch panel. The set of keys 118includes, for example, various types of keys and a controller to detectoperations associated with the various types of keys.

The CPU 115 controls the entire operation of the control panel 16 byreading a program stored in the ROM to the RAM and executing the readprogram. By controlling the operation of the control panel 16, the CPU115, for example, switches display contents to be displayed on the LCDof the display 117, according to a user's operation to operating devicesincluding the various types of keys of the set of keys 118 and the touchpanel of the display 117.

The CPU 115 is communicably connected to the controller 11. The CPU 115sends data, which is input due to the user's operation to the operatingdevice, to the controller 11, if necessary.

With the configuration described above, the central power supply switch15 supplies power from the PSU 14 to the control panel 16. The controlpanel 16 transitions to a power-saving mode, namely the power-savingstate, when the power supply from the central power supply switch 15 isstopped. In the power-saving state, the CPU 115, for example,transitions from the normal state to a sleep state and stops the powersupply to the LCD of the display 117.

The facsimile communication device 17 is a module that performscommunication via a telephone line. The facsimile communication device17 transitions to the power-saving mode to be in, for example, the sleepstate when the power supply from the central power supply switch 15 isstopped.

The data storage device 18 is a nonvolatile storage device that is usedto store image data to be printed out and the like. The data storagedevice 18 transitions to the power-saving mode and the power supply toat least a part of the data storage device 18 is stopped when the powersupply from the central power supply switch 15 is stopped.

The image reading device 19 includes, for example, an automatic documentfeeder (ADF), a scanner, and a controller that controls componentsincluding the ADF and the scanner. Image data obtained by reading adocument with the scanner can be sorted in the data storage device 18.The image reading device 19 transitions to the power-saving mode and thepower supply to, for example, the ADF and the scanner is stopped whenthe power supply from the central power supply switch 15 is stopped. ACPU of the controller transitions to the sleep state.

The image forming device 20 forms an image on a recording medium withsuch as an electrophotographic method. The image forming device 20includes a group of electronic components including a plurality ofmotors, a plurality of solenoids, and a plurality of sensors, a heater,and a control circuit. The image forming device 20 transitions to thepower-saving mode, and the components including the heater stop driving,when the power supply from the central power supply switch 15 isstopped.

The controller 11 controls each of the power supply switches 15 a of thecentral power supply switch 15. The controller 11 includes a main memory102, a main CPU peripheral circuit 103 including a main CPU 104, and asub CPU peripheral circuit 105 including a sub CPU 107, as illustratedin FIG. 1. The main CPU 104 corresponds to a first processor, and thesub CPU 107 corresponds to a second processor in the embodiment.

The main CPU peripheral circuit 103 includes, for example, a ROM storingfirmware and a power supply circuit to supply the power to the main CPU104. The data storage device 18, described above, stores an operatingsystem (OS), various types of applications/programs, etc. that areexecuted by the main CPU 104. The main CPU 104 reads the firmware storedin the ROM to the main memory 102, and then reads anapplication/program, which is to be executed, to the main memory 102 toexecute the application/program.

The main CPU 104 is connected to each of the components 16 to 20 by asignal line, as illustrated in FIG. 1. This allows the main CPU 104 tocontrol each of the components 16 to 20 directly after the OS or theapplication/program is activated.

The sub CPU peripheral circuit 105 includes a network interfacecontroller (NIC) 106 and a non-volatile random access memory (NVRAM)108, in addition to the sub CPU 107.

The NIC 106 is a communication device that communicates with the network30. The NIC 106 outputs data received from the network 30 to the sub CPU107, and sends data received from the sub CPU 107 to the network 30according to an instruction of the sub CPU 107.

The NVRAM 108 is a non-volatile memory that stores various types ofprograms executed by the sub CPU 107 and various types of data. The subCPU 107 sends and receives data via the NIC 106 by executing the programread from the NVRAM 108.

The sub CPU 107 is connected to each of the eco switch 12, the centralpower supply switch 15, the main CPU 104, the control panel 16, and thefacsimile communication device 17, in addition to the NIC 106. The subCPU 107 monitors the operation to the eco switch 12 performed by theuser, and also monitors data output from each of the main CPU 104, thecontrol panel 16, and the facsimile communication device 17.

Data output from each of the eco switch 12, the control panel 16, andthe facsimile communication device 17 is actually, for example, aninterrupt, or interrupt request. In detecting the operation to the ecoswitch 12, the sub CPU 107 controls each of the power supply switches 15a of the central power supply switch 15 to be switched between open andclosed. As a result of this event, each of components 16 to 20transitions from the operating mode to the power-saving mode or from thepower-saving mode to the operating mode each time the eco switch 12 isoperated.

Additionally, when the control panel 16 or the facsimile communicationdevice 17 generates the interrupt, the sub CPU 107 checks whether eachpower supply switch 15 a of the central power supply switch 15 is openor closed. At this time, if determining that the power supply switch 15a is in an open state (off state), the sub CPU 107 switches the state ofthe power supply switch 15 a to a closed state (on state). Through this,the sub CPU 107 can cause each of the components 16 to 20 to transitionfrom the power-saving mode to the operating mode, in response to theinterrupt generated by the control panel 16 or the facsimilecommunication device 17.

The control panel 16 can generate the interrupt when being operated bythe user. The facsimile communication device 17 can generate theinterrupt when receiving a call.

The sub CPU 107 sends and receives data to and from the main CPU 104.The sub CPU 107 can process data that requires a relatively low load tobe processed from the data received by the NIC 106. The sub CPU 107,accordingly, inputs, or receives, the data that the sub CPU 107 canprocess from the NIC 106 and processes the data assigned to the sub CPU107 to process, and then outputs the processed data, which is to besent, to the NIC 106. That is, the sub CPU 107 outputs to the main CPU104 data that the sub CPU 107 cannot process from the data received bythe NIC 106. The data that the sub CPU 107 cannot process is related toprocessing requiring a relatively high load. Such processing includes,for example, copying and printing, which are main processing operationsperformed by the image forming apparatus 1, and this processing isdefined as target processing that is targeted for execution by the mainCPU 104. On the other hand, the processing that the sub CPU 107 canperform, namely processing requiring a relatively low load includes, forexample, checking of presence of devices on the network 30, namelyaddress resolution protocol (ARP) response, and checking of conductivestate, and an internet protocol (IP) address of the devices in thenetwork 30. This processing is defined as secondary processing that isnot targeted for execution by the main CPU 104.

The embodiment provided with the sub CPU 107, which processes some ofthe data received by the NIC 106, allows the main CPU 104 to stay in thesleep state for a long time compared to a configuration without the subCPU 107. The number of types of processing that the sub CPU 107 canperform is small, and a load associated such processing is relativelylow. Accordingly, a device that consumes less power than the main CPU104 consumes, can be used as the sub CPU 107. As described above, theduty ratio of the main CPU 104 is reduced because the main CPU 104 isstaying in the sleep state longer, and thus the embodiment can reduce anamount of power consumption as a whole, even though the sub CPU 107 isimplemented.

The data that the sub CPU 107 cannot process is processed by the mainCPU 104. If the data is to be sent after being processed, the main CPU104 outputs the data to the sub CPU 107 after processing and instructsthe sub CPU 107 to send the data. Then the sub CPU 107 sends the datafrom the main CPU 104 to the network 30 via the NIC 106.

Accordingly, the interrupts due to the operation to the eco switch, thedata received by the NIC 106 and which requires a relatively low load tobe processed, namely the data other than the target data, and theinstruction from the main CPU 104 are included in the secondaryprocessing that is performed by the sub CPU 107, but not by the main CPU104.

As described above, each device connected to the network 30 checks anoperating state of other devices at a predetermined time. The data thatthe sub CPU 107 processes, namely the secondary processing that isperformed by the sub CPU 107 includes, for example, a response to amessage for checking the operating state. It is also possible that thesub CPU 107 sends the message and processes the response to the message.Such processing performed by the sub CPU 107 is also the secondaryprocessing, which is not performed by the main CPU 104.

The main CPU 104 has at least a suspend function and an operating speedadjustment function as the power-saving function. With the suspendfunction, the main CPU 104 saves a state of processing in a memory, andtransitions to a suspend mode, which is the sleep state, in response toto an instruction of the user or an idle state that continues for acertain period. With the operating speed adjustment function, clockfrequency is fixed to frequency set in advance, or the clock frequencyis dynamically changed according to a CPU usage ratio (weight of aload), thereby reducing the amount of the power consumption.

The main CPU 104 that previously transitions to the sleep state returnsto the operating state (operating mode) in response to some of theinterrupts but not all of the interrupts. In the configuration asillustrated in FIG. 1, such interrupts that can be factors that awakenthe main CPU 104 include ones due to the sub CPU 107 associated with thedata transfer of the NIC 106, due to (the CPU 115 of) the control panel16, due to the call to the facsimile communication device 17, and due toa real time clock (RTC). Here in the description, it is assumed that theinterrupts, which can be the factors that awaken the main CPU 104, dueto external factors, namely the interrupts except for the interrupt dueto the RIC, are involved with the sub CPU 107.

The OS executed by the main CPU 104 supports the power-saving function.The OS is implemented with a plurality of types of adjusters(governors), and the adjusters to be activated can be switched. In theembodiment of the disclosure, the adjusters are used for managing astate transition of the main CPU 104 as described below.

FIG. 2 is an illustration of the state transition of the main CPU 104according to the embodiment. Here, the states of the main CPU 104 afterstart-up are classified into three states (modes) including a suspendmode ST3, a power-saving mode ST4, and a high performance mode ST5.

The high performance mode ST5 is a mode, which is included in theoperating mode, in which the main CPU 104 operates with the highestclock frequency. In the mode ST5, the amount of power consumption of themain CPU 104 is not reduced.

In the suspend mode ST3, the main CPU 104 is in the sleep state andcannot perform processing. The amount of power consumption in thesuspend mode ST3 can be reduced to the minimum. The power-saving modeST4 is a mode, which is included in the operating mode in addition tothe high performance mode ST5, in which processing can be performed.

Besides the three states mentioned above, there are a plug off state ST1and a shutdown state ST2. The plug off state ST1 is a state in which theimage forming apparatus is disconnected from the external power supply(e.g. commercial power supply), and the power supply from the externalpower supply is stopped. The shutdown state ST2 is a state in which thepower supply to the image forming apparatus 1 is stopped with theapparatus still plugged in. Transitions between these states areperformed under conditions described below.

By connecting the image forming apparatus 1 to the external power supply(e.g., commercial power supply), the main CPU 104 transitions from theplug off state ST1 to the shutdown state ST2. In disconnecting the imageforming apparatus 1 in the shutdown state ST2 from the external powersupply, the main CPU 104 transitions to the plug off state ST1.

When the user operates with the main power supply switch 13 in theshutdown state ST2, the power supply from the external power supplystarts. This causes the main CPU 104 to transition to the highperformance mode ST5 to start up. Because a start-up time is desirablyshort, the main CPU 104 transitions to the high performance mode ST5. Inresponse to an instruction of the shutdown from the user during the highperformance mode ST5, the main CPU 104 transitions to the shutdown stateST2.

In the operating mode, the clock frequency is changed dynamicallyaccording to a usage rate (the load) of the main CPU 104 in accordancewith control of the activated adjuster (OS). Due to this, the transitionbetween the high performance mode ST5 and the power-saving mode ST4 isperformed according to the load. Additionally, the main CPU 104transitions from the operating mode, which is the high performance modeST5 or the power-saving mode ST4 to the suspend mode ST3, in response tothe idle state that continues for a certain period.

In the suspend mode ST3, the user can shut down the image formingapparatus 1. The shutdown is one of several selections, and the statecan transition from the suspend mode ST3 to the power-saving mode ST4with the shutdown.

Return factors for transitioning from the suspend mode ST3 to thepower-saving mode ST4 include an interrupt due to external factors suchas data reception of the NIC 106 and the interrupt due to the RTC. Inthe embodiment, a destination of the transition from the suspend modeST3 to the operating mode due to such return factors is limited to thepower-saving mode ST4.

In shortening processing time, the higher the performance is, the moredesirable. However, the higher the performance is, the larger the amountof power consumption of the main CPU 104 becomes. To deal with this, theclock frequency to operate the main CPU 104 is required to varyaccording to the load.

However, it is not always possible to estimate an actual load inprocessing of the main CPU 104 correctly, because the load depends on,for example, types of the processing or types of data used for theprocessing. Considering this, in transitioning from the suspend mode ST3to the high performance mode ST5, the performance may be excessivelyhigh. Operating the main CPU 104 with the excessively high performanceincreases an unnecessary amount of power consumption, even if it is onlytemporarily. To cope with this, in the embodiment, the main CPU 104transitions to the power-saving mode ST4 when returning from the suspendmode ST3 to the operating mode.

By transitioning to the power-saving mode ST4, the amount of powerconsumption can be reduced compared to transitioning to the highperformance mode ST5. Even if the load of processing is relatively highfor the power-saving mode ST4, the power-saving mode ST4 can transitionto the high performance mode ST5, and the processing is dealt with. Thistransition can be performed in a short time. As described above, thetransition from the suspend mode ST3 to the power-saving mode ST4 canappropriately reduce the amount of power consumption according to theactual load.

FIG. 3 is a diagram illustrating an example of change in the amount ofpower consumption of the main CPU over time. In FIG. 3, terms of“suspend mode”, “return processing”, “power-saving mode”, and “highperformance mode” are used to present levels of the amount of powerconsumption. The “suspend mode”, the “power-saving mode”, and the “highperformance mode” represent the levels of amount of power consumption inthe suspend mode ST3, the power-saving mode ST4, and the highperformance mode ST5, respectively. The “return processing” representsthe level of the amount of power consumed in transitioning from thesuspend mode ST3 to the power-saving mode ST4.

In the example illustrated in FIG. 3, when the return factor occurs at afirst time, the state transitions to the power-saving mode after thereturning processing, and then transitions to the suspend mode ST3. Onthe other hand, in occurring the return factor at a second time, thestate transitions to the high performance mode ST5 after the returningprocessing and the power-saving mode ST4. This indicates that the returnfactor occurring at the second time is associated with processingrequiring a large load that cannot be dealt with in the power-savingmode ST4.

After that, the state transitions from the high performance mode ST5 tothe power-saving mode ST4, and then from the power-saving mode ST4 tothe suspend mode ST3. This indicates possibility that the load ofprocessing, which is due to the second return factor, becomes smaller byperforming the processing, or processing requiring smaller load isperformed after the processing, which is due to the second returnfactor, is completed.

As described in FIG. 3, the main CPU 104 transitions further to the highperformance mode ST5 according to the load of processing to be performedeven when, or after, transitioning from the suspend mode ST3 to thepower-saving mode ST4. Such transition allows the main CPU 104 tooperate with appropriate performance according to the load of processingand reduce the amount of power consumption in an appropriate way.

The sub CPU 107 executes a program 108 a stored in the NVRAM 108,thereby generating the interrupt that causes the main CPU 104 to returnto the power-saving mode ST4. An overall process performed by the subCPU 107 due to the execution of the program 108 a is described in detailwith reference to a flowchart of FIG. 4 below.

The sub CPU 107 keeps operating to process data, for example, receivinga message from the NIC 106. The sub CPU 107, accordingly, repeatsperforming the process of FIG. 4 during the power supply of the imageforming apparatus 1 is ON.

The sub CPU 107, which passes control to the program 108 a, firstlydetermines whether there is an input (S41). If there is operation to ecoswitch 12 or the control panel 16, or data received by the NIC 106, acall received by the facsimile communication device 17, an instructionfrom the main CPU 104, or the like, such a condition is reported to thesub CPU 107 as the interrupt. On receiving such a notification, the subCPU 107 determines there is an input, so that the determination of theS41 is YES and the process continues to S42. On the contrary, if thereis no notification, the determination of the S41 is NO and the processperforms the determination processing of S41 again.

In S42, the sub CPU 107 determines if the sub CPU 107 can process theinput. As described above, the operation of the user to the eco switch12, some of the data (messages) received by the NIC 106, and theinstructions from the main CPU 104 (mainly data transfer instruction viathe NIC 106) are the secondary processing that the sub CPU 107 canprocess in alternative to the main CPU 104. The operation to the ecoswitch 12 or the data, which is to be processed by the sub CPU 107, isinput from the NIC 106 or the main CPU 104, the determination of S42 isYES, and the process continues to S43. On the other hand, when theoperation to the control panel 16, the call received by the facsimilecommunication device 17, or the data, which cannot be processed by thesub CPU 107, is received by the NIC 106, the determination of S42 is NO,and the process continues to S44.

In S43, the sub CPU 107 performs the processing associated with theoperation to the eco switch 12 or the data input from the NIC 106 or themain CPU 104. According to the processing of the sub CPU 107 in S43, anopen/close operation of each of the power supply switches 15 a includedin the central power supply switch 15, the data transfer using the NIC106 or the like is performed. After the processing of S43, the processreturns to the S41, described above.

In S44, the sub CPU 107 determines if the power supply to the main CPU104 is stopped (OFF), which means that if the main CPU 104 is in thesuspend mode ST3 (sleep state). If the power supply to the main CPU 104is stopped, the determination of S44 is YES, and the process continuesto S46. If the power supply to the main CPU 104 is performed, thedetermination of S44 is NO, and the process continues to S45.

In S45, the sub CPU 107 requests the main CPU 104 for processingaccording to content of the input. For example, when the NIC 106receives the data that the sub CPU 107 cannot deal with, the sub CPU 107requests the main CPU 104 to process the data by outputting the data tothe main CPU 104. After that, the process returns to S41, which isdescribed above.

In S46, the sub CPU 107 performing processing to cause the main CPU 104to transition to the power-saving mode ST4, by, for example, generatingthe interrupt. If the data that cannot be processed with the sub CPU 107is input, the sub CPU 107 requests the main CPU 104 for processing ofthe data after the transition to the power-saving mode ST4. After that,the process returns to S41, which is described above.

With the power-saving mode ST4 that is transitioned from the suspendmode ST3, the adjuster that has clock frequency lower than the originalhighest clock frequency is activated. For example, after the transitionto the power-saving mode ST4, the sub CPU 107 activates other adjusterthat changes the clock frequency according to the load, according to acertain elapsed time, with an upper limitation of the highest clockfrequency of the adjuster. As a result, the main CPU 104 can operatealong with the transition (mode transition) of the amount of powerconsumption, as described in FIG. 3. The switching of the other adjusteris performed, for example, due to an output of command processed by theOS.

As described above, the sub CPU 107 executing the program 108 a detectsprocessing that is to be performed by the main CPU 104, and also managesthe transition of the state of the main CPU 104 from the suspend modeST3 to the power-saving mode ST4. That is, the sub CPU 107 serves as adetector and a transition controller in the embodiment.

The embodiment is described by applying the disclosure to the imageforming apparatus 1, however an applicable information processingapparatus is not limited to the image forming apparatus. The embodimentof the disclosure can be used widely with the information processingapparatus that is implemented with one or more of first processors suchas one or more of CPUs (each corresponding to the main CPU 104 in theembodiment), and one or more of second processors (each corresponding tothe sub CPU 107 in the embodiment) that consume an amount of power lessthan the first processors.

The first processor and the second processor may be sealed in the samepackage. implementing the first processor and the second processor inthe same sealed package, namely integrating the first processor and thesecond processor on a system on chip, can reduce in size and costsbecause of reduction in the number of components.

With the power-saving mode ST4 that is transitioned from the suspendmode ST3, the highest clock frequency is lower than the original highestclock frequency, however, the power-saving mode ST4 is not limited to(or operates) the clock frequency. When the main CPU 104 is a multi-coreCPU that is implemented with a plurality of cores, which executeprocessing, the power-saving mode ST4 may be a mode in which the numberof cores operating the processing may be reduced instead of limiting theclock frequency, or in addition to the limitation of the clockfrequency. With the multi core CPU, the number of selections that areways to reduce the amount of power consumption increase. This can reducethe amount of power consumption appropriately by selecting anappropriate way. The power-saving mode ST4 may be any mode as long asthe amount of power consumption is smaller than the high performancemode ST5, in which the amount of the power consumption is the highest.

Additionally, in the description of the embodiment, the sleep state,from which the state transitions to the power-saving mode ST4,corresponds to the suspend mode ST3, however, the sleep state is notlimited to the suspend mode ST3. The sleep state in the description isused as a state in which the CPU cannot perform the processing, and alsoincludes a stop mode in which the processing cannot be performed.Considering this, the sleep state may be not only the suspend mode ST3,but also a different mode from the suspend mode ST3. The sleep state mayinclude a plurality of modes, which are selectable.

Although the exemplary embodiments of the disclosure have been describedand illustrated above, such description is not intended that thedisclosure be limited to the illustrated embodiments. Numerousadditional modifications and variations are possible in light of theabove teachings. It is therefore to be understood that within the scopeof the appended claims, the embodiments may be practiced otherwise thanas specifically described herein. For example, elements and/or featuresof different illustrative embodiments may be combined with each otherand/or substituted for each other within the scope of this disclosureand appended claims.

What is claimed is:
 1. An information processing apparatus to performprocessing, comprising: an image forming device including a fixing unit;a display; a data storage; a first processor operable to perform firstprocessing and second processing in one of a plurality of operatingstates, the plurality of operating states including a normal state inwhich each of the image forming device, display and data storage areoperable and a power-saving state in which each of the image formingdevice, display and data storage are not operable, the power-savingstate being a state in which the first processor consumes relativelyless power than the normal state; and a second processor operable in asleep state in which no power is supplied to the first processor, toperform the second processing while consuming relatively less power thanthe first processor consumes, the second processor being unable toperform the first processing and being further configured to: detect theprocessing to be performed by the information processing apparatus asthe first processing or the second processing; execute detectedprocessing when the detected processing is second processing; and cause,upon the first processor being in the sleep state in which a powersupply to the first processor is stopped and the second processor isoperable and upon the processing detected being processing that cannotbe performed by the second processor, the first processor to transitionfrom the sleep state directly to the power-saving state and dynamicallyadjust a clock frequency according to a load of the processing to beperformed, the adjusted clock frequency being lower than a maximum clockfrequency of the first processor, to perform the first processing. 2.The information processing apparatus of claim 1, wherein the firstprocessor and the second processor are sealed in a same package.
 3. Theinformation processing apparatus of claim 2, wherein the first processorcomprises a plurality of cores to perform the first processing andsecond processing.
 4. The information processing apparatus of claim 1,wherein the sleep state is a state in which the first processor isconfigured to operate with a clock frequency relatively lower than aclock frequency of the normal state.
 5. The information processingapparatus of claim 1, wherein the first processing includes processingrequiring a relatively higher load of processing, compared to the secondprocessing.
 6. The information processing apparatus of claim 1, whereinthe second processor is further configured to perform the secondprocessing, upon the processing detected being second processing.
 7. Theinformation processing apparatus of claim 1, wherein in the operatingmode, the information processing apparatus transitions between thenormal and the power-saving mode according to a usage rate of the firstprocessor.
 8. A method of processing of information, comprising:providing a first processor and a second processor, the first processorbeing operable to perform first processing and second processing in oneof a plurality of operating states, the plurality of operating statesincluding a normal state in which each of an image forming device, adisplay and a data storage are operable and a power-saving state inwhich each of the image forming device, the display and the data storageare not operable, the power-saving state being a state in which thefirst processor consumes relatively less power than the normal state,and the second processor being operable in a sleep state in which nopower is supplied to the first processor, to perform the secondprocessing while consuming relatively less power than the firstprocessor consumes and being unable to perform the first processing;detecting processing of information to be performed as the firstprocessing or the second processing; executing detected processing whenthe detected processing is second processing; and controlling, upon thefirst processor being in the sleep state in which a power supply isstopped and upon the processing of information detected being processingthat cannot be performed by the second processor, the first processor todirectly transition from the sleep state to the power-saving state anddynamically adjusting a clock frequency according to a load of theprocessing to be performed, the adjusted clock frequency being lowerthan a maximum clock frequency of the first processor, to perform thefirst processing.
 9. The method of processing information of claim 8,wherein the first processor comprises a plurality of cores to performthe first processing and second processing.
 10. The method of processinginformation of claim 8, wherein the sleep state is a state in which thefirst processor is configured to operate with a clock frequencyrelatively lower than a clock frequency of the normal state.
 11. Themethod of processing information of claim 8, further comprising:detecting, via the second processor, the processing of information to beperformed as the second processing; and performing, via the secondprocessor, the second processing upon the processing of informationdetected being second processing.
 12. The method of processinginformation of claim 8, wherein the first processing includes processingrequiring a relatively higher load of processing, compared to the secondprocessing.
 13. The method of processing information of claim 8, whereinthe second processing includes determining an operating state of thefirst processor.
 14. A method of processing, in an informationprocessing apparatus to perform processing including a first processorand a second processor, the second processor being able to perform atleast some of the processing while consuming relatively less power thanthe first processor consumes, the method comprising: detecting, via thesecond processor, processing to be performed; executing detectedprocessing when the detected processing is the second processor is ableto perform; determining, via the second processor, an operating state ofthe first processor, and controlling the first processor to transitionfrom a sleep operating state to a first power operating state in whicheach of an image forming device, a display and a data storage are notoperable and from the first power operating state to a second poweroperating state in which each of the image forming device, the displayand the data storage are operable and dynamically adjusting a clockfrequency according to a load of the processing to be performed, theadjusted clock frequency being lower than a maximum clock frequency ofthe first processor, in which the first processor is configured toperform the processing detected, upon the processing detected beingprocessing that the second processor is unable to perform and upon theoperating state determined being the sleep state.
 15. The method ofprocessing information of claim 14, further comprising: performing theprocessing detected, via the second processor, upon the processingdetected being processing that the second processor is able to perform.16. The method of processing information of claim 14, wherein the sleepoperating state is a state in which the first processor is configured tooperate with a clock frequency relatively lower than a clock frequencyof the power operating state.
 17. The method of processing informationof claim 14, wherein the processing that the second processor is able toperform includes processing requiring a relatively higher load ofprocessing, compared to other processing.